| CPC G06F 3/0626 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/3459 (2013.01)] | 20 Claims |

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1. A page buffer, comprising:
a first latch configured to store program verification information;
a second latch configured to store first bit line forced information;
a dynamic latch configured to store second bit line forced information, wherein the first bit line forced information is different from the second bit line forced information, and the dynamic latch comprises a control switch coupled to the second latch, wherein the dynamic latch is configured to store information through a capacitor to which the control switch is coupled;
a first precharge circuit configured to generate a first forced programming voltage, wherein the first precharge circuit is coupled to a bit line through a sensing node; and
a second precharge circuit configured to generate a second forced programming voltage, wherein the second precharge circuit is coupled to the bit line through the sensing node, wherein the second precharge circuit comprises a first p-channel Metal-Oxide-Semiconductor (PMOS) transistor and a second PMOS transistor connected in series between a supply voltage and the sense node, wherein a gate of the first PMOS transistor is coupled to the dynamic latch.
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