| CPC G06F 3/0619 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |

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1. A non-volatile memory device, comprising:
a control circuit configured to connect to an array of non-volatile memory cells, the array including a first NAND string comprising a plurality of memory cells each connected in series to a corresponding word line, between a first bit line and a source line, and connected to the first bit line through a drain side select gate and to the source line through a source side select gate, the control circuit configured to perform a program operation on a selected memory cell of the first NAND string, where, to perform the program operation, the control circuit is configured to:
apply a programming pulse to the corresponding word line connected to the selected memory cell; and
prior to applying the programming pulse to the corresponding word line connected to the selected memory cell, perform a pre-charge operation on the first NAND string in which the control circuit is configured to:
bias the corresponding word lines of the first NAND string to a low voltage level;
bias the drain side select gate and the source side select gate of the first NAND string to be off; and
while the corresponding word lines of the first NAND string are biased to the low voltage level and the drain side select gate and the source side select gate of the first NAND string are biased to be off, bias one or both of the first bit line and the source line to a first voltage level for a first interval.
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