US 12,229,406 B2
Speed bins to support memory compatibility
Eric V. Pohlmann, Boise, ID (US); and Neal J. Koyle, Nampa, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 20, 2023, as Appl. No. 18/390,820.
Application 18/390,820 is a continuation of application No. 17/585,253, filed on Jan. 26, 2022, granted, now 11,886,702.
Claims priority of provisional application 63/145,296, filed on Feb. 3, 2021.
Prior Publication US 2024/0126434 A1, Apr. 18, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0607 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method at a host device, comprising:
reading a value of a register comprising serial presence detect (SPD) data of a memory module, the SPD data indicative of a first value of a timing constraint for operating the memory module at a corresponding first clock rate, the first value of the timing constraint and the first clock rate associated with a first speed bin;
selecting, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and a second value of the timing constraint, wherein the second clock rate is lower than the first clock rate and the second value of the timing constraint is higher than or equal to the first value of the timing constraint; and
communicating with the memory module according to the second speed bin.