	US 12,229,404 B2
	Memory system and control method thereof
Kazuya Kitsunai, Kawasaki (JP); Shinichi Kanno, Tokyo (JP); Hirokuni Yano, Tokyo (JP); Toshikatsu Hida, Kawasaki (JP); and Junji Yano, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Dec. 7, 2023, as Appl. No. 18/532,267.
Application 18/532,267 is a continuation of application No. 17/591,812, filed on Feb. 3, 2022, granted, now 11,893,237.
Application 17/591,812 is a continuation of application No. 16/730,329, filed on Dec. 30, 2019, granted, now 11,287,975, issued on Mar. 29, 2022.
Application 16/730,329 is a continuation of application No. 15/895,204, filed on Feb. 13, 2018, granted, now 10,558,360, issued on Feb. 11, 2020.
Application 15/895,204 is a continuation of application No. 15/270,939, filed on Sep. 20, 2016, granted, now 9,933,941, issued on Apr. 3, 2018.
Application 15/270,939 is a continuation of application No. 14/923,128, filed on Oct. 26, 2015, granted, now 9,483,192, issued on Nov. 1, 2016.
Application 14/923,128 is a continuation of application No. 14/683,286, filed on Apr. 10, 2015, granted, now 9,280,292, issued on Mar. 8, 2016.
Application 14/683,286 is a continuation of application No. 14/455,680, filed on Aug. 8, 2014, granted, now 9,026,724, issued on May 5, 2015.
Application 14/455,680 is a continuation of application No. 12/778,484, filed on May 12, 2010, granted, now 8,886,868, issued on Nov. 11, 2014.
Application 12/778,484 is a continuation of application No. 12/552,422, filed on Sep. 2, 2009, granted, now 8,015,347, issued on Sep. 6, 2011.
Application 12/552,422 is a continuation of application No. PCT/JP2008/066508, filed on Sep. 8, 2008.
Claims priority of application No. 2007-339946 (JP), filed on Dec. 28, 2007.
Prior Publication US 2024/0111416 A1, Apr. 4, 2024
Int. Cl. G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/08 (2016.01)

CPC G06F 3/0604 (2013.01) [G06F 3/0616 (2013.01); G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0647 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0685 (2013.01); G06F 12/0246 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7205 (2013.01); G06F 2212/7211 (2013.01)]

21 Claims

1. A portable electronic device comprising:

a housing;

a display mounted on the housing;

a printed circuit board accommodated in the housing, the printed circuit board including a bus;

a memory device mounted on the printed circuit board and connected to the bus;

a main memory mounted on the printed circuit board and connected to the bus; and

processor circuitry mounted on the printed circuit board and connected to the bus, the processor circuitry being configured to:

manage a logical address of data to be written to the memory device;

issue a write request to the memory device; and

transfer first data from the main memory via the bus to the memory device, wherein

the memory device includes:

an interface;

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, the plurality of blocks including at least a first block, a second block, and a third block; and

a controller electrically connected to the nonvolatile memory and configured to:

when the number of data erase operations performed on the first block is smaller than the number of data erase operations performed on the second block, copy second data from the first block to the second block; and

when the copying is not performed, write the first data to the third block, the first data being data that is received from the processor circuitry through the interface and has not been stored in the nonvolatile memory, and

the processor circuitry is further configured to:

issue a read request to the memory device;

read the first data from the memory device; and

store the read first data into the main memory via the bus.