US 12,229,253 B2
Devices and methods to secure a system on a chip
Asif Rashid Zargar, Greater Noida (IN); Gilles Eyzat, Claix (FR); and Charul Jain, Delhi (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH); and STMicroelectronics (Alps) SAS, Grenoble (FR)
Filed by STMicroelectronics (Alps) SAS, Grenoble (FR); and STMicroelectronics International N.V., Geneva (CH)
Filed on Jun. 7, 2021, as Appl. No. 17/340,164.
Claims priority of application No. 2006059 (FR), filed on Jun. 10, 2020.
Prior Publication US 2021/0390180 A1, Dec. 16, 2021
Int. Cl. G06F 21/55 (2013.01)
CPC G06F 21/552 (2013.01) [G06F 2221/034 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A method for operating a system on a chip, the method comprising:
having a set of one-time programmable memory elements, the set comprising a first valid configuration, a second valid configuration, and a plurality of invalid configurations;
having a programming indicator set to a first value before the set of one-time programmable memory elements is programmed, the programming indicator used to detect a programming state of the set of one-time programmable memory elements;
programming the set of one-time programmable memory elements to the first valid configuration, a value of the programming indicator being independent of an initial configuration of the set of one-time programmable memory elements;
permanently setting the programming indicator to a second value in response to the set of one-time programmable memory elements leaving the first valid configuration;
detecting a security threat to the system on a chip in response to the programming indicator being set to the second value and the set of one-time programmable memory elements being set to an invalid configuration of the plurality of invalid configurations:
setting a security level of the system on a chip to a first security level in response to the programming indicator being in the first value;
setting the security level of the system on a chip to a second security level in response to the set of one-time programmable memory elements being in the second valid configuration; and
generating an interrupt signal in response to the programming indicator being set to the first value and the set of one-time programmable memory elements being in the second valid configuration.