US 12,229,252 B2
Microprocessor that prevents store-to-load forwarding between different translation contexts
John G. Favor, San Francisco, CA (US)
Assigned to Ventana Micro Systems Inc., Cupertino, CA (US)
Filed by Ventana Micro Systems Inc., Cupertino, CA (US)
Filed on Jun. 9, 2023, as Appl. No. 18/207,964.
Application 18/207,964 is a continuation of application No. 17/185,765, filed on Feb. 25, 2021, granted, now 11,803,637.
Application 17/185,765 is a continuation in part of application No. 16/937,392, filed on Jul. 23, 2020, granted, now 11,755,731.
Prior Publication US 2023/0315838 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 29/06 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/455 (2018.01); G06F 21/54 (2013.01); G06F 21/55 (2013.01); G06F 21/56 (2013.01)
CPC G06F 21/54 (2013.01) [G06F 9/30043 (2013.01); G06F 9/3842 (2013.01); G06F 9/45558 (2013.01); G06F 21/554 (2013.01); G06F 21/566 (2013.01); G06F 2009/45587 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method of mitigating side channel attacks (SCAs) that exploit store-to-load forwarding operations on a pipelined, speculative out-of-order execution processor, the method comprising:
detecting an event that updates the translation context (TC); and
at least for a subset of TC updates that cause TC changes from a first TC to a second TC that is different from the first TC, preventing store-to-load forwarding to load instructions dispatched in the second TC that are dependent on store instructions dispatched in the first TC;
wherein a TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a translation regime (TR), a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM; and
wherein a TC update occurs during execution of an instruction that expressly updates the TC, or some component thereof.