| CPC G06F 21/54 (2013.01) [G06F 9/45558 (2013.01); G06F 12/0864 (2013.01); G06F 12/0882 (2013.01); G06F 21/554 (2013.01); G06F 21/566 (2013.01); G06F 21/79 (2013.01); G06F 2009/45587 (2013.01); G06F 2212/7201 (2013.01)] | 18 Claims |
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1. A system, comprising:
at least one processor; and
a cached memory subsystem comprising a cache memory and a main memory, the main memory storing program instructions that when executed cause the at least one processor to implement a virtual memory manager configured to:
responsive to a request to map a physical memory page to a virtual memory page:
reserve a plurality of physical memory pages of the main memory for the virtual memory page, the plurality of physical memory pages comprising a first physical memory page and second physical memory page, wherein respective ones of the plurality of physical memory pages comprise respective starting memory addresses that differ within a range of memory address bits, the range of memory address bits determined according to a selectivity of locations within the cache memory; and
map the virtual memory page to the first physical memory page of the reserved plurality of physical memory pages; and
responsive to a memory remapping event, remap the virtual memory page from the first physical memory page to the second physical memory page, reserved responsive to the request to map the physical memory page to the virtual memory page, to change a mapping of respective locations of the cache memory to locations of the virtual memory page according to differences in the respective ranges of address bits of the first physical memory page and the second physical memory page.
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