US 12,229,075 B2
Transaction layer packet format
David J. Harriman, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 29, 2023, as Appl. No. 18/478,595.
Application 18/478,595 is a continuation of application No. 16/831,634, filed on Mar. 26, 2020, granted, now 11,775,470.
Claims priority of provisional application 62/938,096, filed on Nov. 20, 2019.
Prior Publication US 2024/0028551 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/4282 (2013.01) [G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first die comprising:
processor circuitry; and
a port to couple to another second die over a link, wherein the port comprises protocol circuitry to generate flit data for a flit mode of a Peripheral Component Interconnect Express (PCIe)-based protocol, wherein the flit data comprises a header, the header comprises an orthogonal header content (OHC) field, the OCH field is encoded to indicate presence of particular OHC in the header, wherein the header further comprises the particular OHC,
wherein the port is to send the flit data on the link to the second die.