US 12,229,069 B2
Accelerator controller hub
Pratik Marolia, Hillsboro, OR (US); Andrew Herdrich, Hillsboro, OR (US); Rajesh Sankaran, Portland, OR (US); Rahul Pal, Bangalore (IN); David Puffer, Tempe, AZ (US); Sayantan Sur, Portland, OR (US); and Ajaya Durg, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 28, 2020, as Appl. No. 17/083,200.
Prior Publication US 2021/0042254 A1, Feb. 11, 2021
Int. Cl. G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4027 (2013.01) [G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An integrated circuit comprising: a hub, including, a host device link (HDL) interface configured to connect the hub to a host via an HDL link coupled between the hub and the host; one or more input-output (IO) interfaces, configured to be connected to an IO device via a direct IO link between an IO interface and the IO device; one or more accelerator link interfaces, configured to be connected to an accelerator via a direct link between an accelerator link interface and the accelerator; a router, operatively coupled to each of the HDL interface, the one or more IO interfaces, and the one or more accelerator link interfaces, wherein the hub is configured to transfer data originating from one or more accelerators connected to the one or more accelerator link interfaces to one or more IO devices connected to the one or more IO interfaces.