| CPC G06F 13/1689 (2013.01) [G06F 13/1621 (2013.01); G06F 13/4068 (2013.01)] | 20 Claims |
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1. An electronic device comprising:
a first memory device, a second memory device, a third memory device, and a fourth memory device;
a memory controller configured to control the first to fourth memory devices;
a first signal line configured to make electrical connection between the memory controller and a first branch point;
a second signal line configured to make electrical connection between the first branch point and a second branch point;
a third signal line configured to make electrical connection between the first branch point and a third branch point, the second and third signal lines being distinct and separate, the second and third branch points being electrically connected to the first branch point in parallel;
a fourth signal line configured to electrically connect the second branch point and the first memory device;
a fifth signal line configured to electrically connect the second branch point and the second memory device, the fourth and fifth signal lines being distinct and separate, the first and second memory devices being electrically connected to the second branch point in parallel;
a sixth signal line configured to electrically connect the third branch point and the third memory device;
a seventh signal line configured to electrically connect the third branch point and the fourth memory device, the sixth and seventh signal lines being distinct and separate, the third and fourth memory devices being electrically connected to the third, branch point in parallel; and
a stub including a first end electrically connected with at least one of the first to seventh signal lines, and a second end being left open-circuit without connection with any other electrical path.
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