US 12,229,060 B2
Memory module with computation capability
Dmitri Yudanov, Rancho Cordova, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 17, 2021, as Appl. No. 17/554,400.
Application 17/554,400 is a continuation of application No. 16/713,989, filed on Dec. 13, 2019, granted, now 11,232,049.
Prior Publication US 2022/0107907 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/4027 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory module, having:
a first bus in the memory module;
a plurality of memory chips connected to the first bus;
a first controller coupled to the first bus;
a second controller coupled to the first bus, wherein the second controller comprises at least one graphics processing unit (GPU); and
at least one interface device coupled to the first bus and configured to communicate input and output data for the memory module; and
facilitate communication among a plurality of instances of the memory module generated via a global shared context implemented by the memory module to facilitate processing of the data proximate to the memory module by the GPU;
at least one arbiter configured to:
queue memory requests to each of the plurality of memory chips for the data; and
resolve at least one conflict when a processor outside of the memory module attempts to access the data in the plurality of memory chips while the first or second controller is accessing the plurality of memory chips;
wherein the first bus is connectable as a part of a second bus to which the processor outside of the memory module is connected; and
wherein the least one interface device is configured to bypass the second bus and the processor.