| CPC G06F 12/1036 (2013.01) [G06F 13/1668 (2013.01); G06F 2212/657 (2013.01)] | 20 Claims |
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1. A heterogeneous processing system, comprising:
switch and bus circuitry;
a host processor coupled to a host memory accessible from the host processor without utilizing the switch and bus circuitry;
a first processor coupled to a first memory accessible from the first processor without utilizing the switch and bus circuitry;
a second processor coupled to a second memory accessible from the second processor without utilizing the switch and bus circuitry; and
a plurality of data transfer resources;
wherein the switch and bus circuitry communicatively couples the host processor, the first processor, the second processor, and the plurality of data transfer resources;
wherein the host processor is configured to, at runtime:
i) detect an application for execution by both the first processor and the second processor,
ii) dynamically select one of a plurality of different data access methods for accessing data between the first and second processors based on user-defined metadata of data passing, including:
source and destination device types,
memory addresses,
bandwidth of application-defined pipeline, and
latency requirement of operation device stages, and
iii) configure the heterogeneous processing system based on the selected data access method;
wherein the plurality of different data access methods for accessing data between the first and second processors include:
a) directly accessing the data in the second memory by the first processor,
b) transferring the data between the first memory and the second memory using a first data transfer resource of the plurality of data transfer resources without passing the data through the host memory, and
c) transferring the data from the second memory to the host memory and then transferring the data from the host memory to the first memory using one or more data transfer resources of the plurality of data transfer resources.
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