US 12,229,054 B2
Reconfigurable caches for improving performance of graphics processing units
Suryanarayana Murthy Durbhakula, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 31, 2023, as Appl. No. 18/194,505.
Prior Publication US 2024/0330195 A1, Oct. 3, 2024
Int. Cl. G06F 12/0897 (2016.01); G06F 12/0891 (2016.01); G06T 1/60 (2006.01)
CPC G06F 12/0897 (2013.01) [G06F 12/0891 (2013.01); G06T 1/60 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus for graphics processing, comprising:
a memory; and
at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to:
monitor, during a first observation interval in a set of observation intervals, an average memory latency for a cache including a first configuration;
calculate, at an end of the first observation interval, a first average memory latency for the first configuration of the cache;
adjust, at a beginning of a second observation interval in the set of observation intervals, the first configuration of the cache to a second configuration of the cache;
calculate, at an end of the second observation interval, a second average memory latency for the second configuration of the cache; and
output an indication of a lowest average memory latency of the first average memory latency for the first configuration or the second average memory latency for the second configuration.