US 12,229,052 B2
System for prefetching data into a cache
Ramkumar Srinivasan, Bangalore (IN); Gerard Williams, Newport Coast, CA (US); and Varun Palivela, Santa Clara, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Apr. 2, 2024, as Appl. No. 18/624,290.
Application 18/624,290 is a continuation of application No. 18/169,118, filed on Feb. 14, 2023, granted, now 12,135,649.
Claims priority of provisional application 63/386,224, filed on Dec. 6, 2022.
Prior Publication US 2024/0248847 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0862 (2016.01); G06F 12/02 (2006.01); G06F 12/123 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 12/0238 (2013.01); G06F 12/123 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A prefetch system for prefetching data into a cache, comprising:
a prefetch control circuit;
a fetch table;
a delta table; and
in response to a signal, the prefetch control circuit configured to:
select a first fetch entry in the fetch table, the first fetch entry comprising a first address for a first memory operation, a set of prefetched memory deltas, and a last prefetched address in the first fetch entry;
access a first delta entry in the delta table based on the first address for the first memory operation and the set of prefetched memory deltas, the first delta entry comprising a next memory delta;
determine a calculated address for prefetching by adding the next memory delta to the last prefetched address in the first fetch entry; and
fetch data based on the calculated address.