US 12,229,051 B2
Memory management device for performing DMA operations between a main memory and a cache memory
Ritesh Banerjee, Bangalore (IN); Jiaxiang Shi, Singapore (SG); and Ingo Volkening, Singapore (SG)
Assigned to Intel Germany GmbH & Co. KG, Neubiberg (DE)
Filed by Intel Germany Gmbh & Co. KG, Neubiberg (DE)
Filed on Dec. 29, 2022, as Appl. No. 18/147,719.
Application 18/147,719 is a continuation of application No. 17/455,220, filed on Nov. 17, 2021, abandoned.
Application 17/455,220 is a continuation of application No. 15/527,138, granted, now 11,354,244, issued on Jun. 7, 2022, previously published as PCT/EP2015/077507, filed on Nov. 24, 2015.
Claims priority of application No. 10201407795P (SG), filed on Nov. 25, 2014.
Prior Publication US 2023/0195633 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0831 (2016.01); G06F 12/0811 (2016.01); G06F 12/1081 (2016.01); G06F 12/08 (2016.01)
CPC G06F 12/0835 (2013.01) [G06F 12/0811 (2013.01); G06F 12/1081 (2013.01); G06F 12/08 (2013.01); G06F 2212/1024 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a main memory;
at least one cache memory;
a memory copy device connectable with the main memory and the cache memory, wherein the memory copy device to access data in the main memory and data in the cache memory, to manage reading and writing data between the main memory and the cache memory, and to maintain data coherence between the main memory and the cache memory; and
an interconnect module coupled to the main memory and the at least one cache memory, wherein the interconnect module is configured to present a request for a Direct Memory Access (DMA) operation to either the main memory or the cache memory based on an address range of a destination memory address.