	US 12,229,044 B2
	Memory devices and methods which may facilitate tensor memory access
Fa-Long Luo, San Jose, CA (US); Jaime Cummins, Bainbridge Island, WA (US); Tamara Schmitz, Scotts Valley, CA (US); and Jeremy Chritz, Seattle, WA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 16, 2022, as Appl. No. 17/888,748.
Application 17/888,748 is a continuation of application No. 17/150,675, filed on Jan. 15, 2021, granted, now 11,422,929.
Application 17/150,675 is a continuation of application No. 16/043,921, filed on Jul. 24, 2018, granted, now 10,956,315, issued on Mar. 23, 2021.
Prior Publication US 2022/0398190 A1, Dec. 15, 2022
Int. Cl. G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0864 (2016.01); G06F 12/0893 (2016.01)

CPC G06F 12/0207 (2013.01) [G06F 12/0223 (2013.01); G06F 12/0292 (2013.01); G06F 12/0864 (2013.01); G06F 12/0893 (2013.01); G06F 12/06 (2013.01); G06F 2212/173 (2013.01); G06F 2212/206 (2013.01); G06F 2212/253 (2013.01)]

21 Claims

1. A method comprising:

generating a sequence of memory addresses based on a memory command;

specifying a set of instructions to access a memory with the sequence of memory addresses, wherein the set of instructions is structured to include an indication of a type of the memory command, and a starting address and a length of data associated with the memory command, and wherein the type of the memory command is selected from a plurality of types, the plurality of types including a diagonal access type, and wherein the diagonal access type causes access only to a plurality of memory cells of the memory arranged diagonally in a matrix; and

performing, according to the sequence of memory addresses, the memory command.