| CPC G06F 11/3419 (2013.01) [G06F 9/542 (2013.01); G06F 11/3024 (2013.01); G06F 11/3409 (2013.01)] | 14 Claims |
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1. An apparatus comprising:
a plurality of latency event counters, each latency event counter associated with a latency event type; and
an evaluation circuit to:
select one or more front end latency events to be counted from a plurality of signaled latency events, and each signaled latency event associated with a latency event type, wherein the fronted latency events are to be selected from one or more of a branch redirection, an instruction translation buffer (ITLB) miss, an instruction cache miss, and an incorrect branch prediction;
generate an update to cause one or more of the plurality of latency event counters to be updated based on the selected one or more latency event signals; and
associate an indication with an operation, the indication based on the plurality of latency event counters, and the indication identifying one or more latency events affecting the operation; and
a pipeline comprising a plurality of pipeline stages including the pipeline stage, and wherein the selecting is performed in response to an indication that one or more of the plurality of pipeline stages is missing information to perform a task.
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