US 12,229,029 B2
Apparatus and method for testing high-speed low-latency interconnect interface (HLII) for silicon interposer
Xiaojie Ma, Wuxi (CN); Xiaochen Hu, Wuxi (CN); Yanfeng Xu, Wuxi (CN); Yuting Xu, Wuxi (CN); Yanfei Zhang, Wuxi (CN); and Yueer Shan, Wuxi (CN)
Assigned to WUXI ESIONTECH CO., LTD., Wuxi (CN)
Filed by WUXI ESIONTECH CO., LTD., Wuxi (CN)
Filed on Jul. 5, 2023, as Appl. No. 18/346,892.
Application 18/346,892 is a continuation of application No. PCT/CN2023/083028, filed on Mar. 22, 2023.
Claims priority of application No. 202211730622.0 (CN), filed on Dec. 30, 2022.
Prior Publication US 2023/0367683 A1, Nov. 16, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 11/22 (2006.01); G06F 11/27 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/27 (2013.01) [G06F 11/2007 (2013.01); G06F 11/221 (2013.01); G06F 13/4282 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An apparatus for testing a high-speed low-latency interconnect interface (HLII) for a silicon interposer, comprising:
a standard test port configured to exchange a standard test instruction;
an asynchronous bypass port configured to directly access an input/output (I/O) port of a channel of a physical layer of the HLII;
a built-in self-test (BIST) engine configured to implement an inter-level loopback testing and a data verification;
a redundant data channel configured to repair a damaged data channel; and
a delay chain testing circuit configured to test a function and a linearity of a delay chain.