US 12,229,006 B2
Integrated circuit and method of operating same
Shih-Lien Linus Lu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,879.
Application 18/362,879 is a continuation of application No. 17/816,085, filed on Jul. 29, 2022, granted, now 11,734,111.
Application 17/816,085 is a continuation of application No. 17/314,716, filed on May 7, 2021, granted, now 11,461,174, issued on Oct. 4, 2022.
Claims priority of provisional application 63/072,534, filed on Aug. 31, 2020.
Prior Publication US 2023/0376378 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 21/55 (2013.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 21/552 (2013.01); G06F 2221/034 (2013.01); G11C 11/1675 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first memory cell array comprising:
a first portion of memory cells configured to store a first set of data; and
a second portion of memory cells configured to store a first inverted set of check bits;
a first set of inverters coupled to the second portion of the memory cells and being configured to receive a second set of check bits, and to generate a third set of check bits in response to the second set of check bits, the third set of check bits being inverted from the second set of check bits, and the second set of check bits corresponds to the first inverted set of check bits stored in the second portion of the memory cells; and
an error correction code (ECC) decoder coupled to the first set of inverters and the first portion of the memory cells, and configured to at least detect or correct an error in at least a second set of data or the third set of check bits thereby generating at least a set of output data and a been-attacked signal, the second set of data corresponds to the first set of data stored in the first portion of the memory cells, and the been-attacked signal indicating a reset attack by a user.