| CPC G06F 11/1044 (2013.01) [H03M 13/45 (2013.01)] | 15 Claims |
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1. A memory system comprising:
a nonvolatile memory that includes a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit; and
a memory controller configured to control the nonvolatile memory, wherein
the nonvolatile memory is configured to:
output, to the memory controller, first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data related to the first bit, the second bit, and the third bit, in response to a first command set received from the memory controller; and
output, to the memory controller, the first hard bit data, the second hard bit data, the third hard bit data, first soft bit data related to the first bit, second soft bit data related to the second bit, and third soft bit data related to the third bit, in response to a second command set received from the memory controller, and
the memory controller is configured to:
in a case where the first command set is transmitted to the nonvolatile memory, perform an error correction process by using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data; and
in a case where the second command set is transmitted to the nonvolatile memory, perform the error correction process by using the first hard bit data, the second hard bit data, the third hard bit data, the first soft bit data, the second soft bit data, and the third soft bit data.
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