US 12,229,003 B2
Memory error detection and correction
Hiroki Noguchi, Hsinchu (TW); Yu-Der Chih, Hsinchu (TW); Hsueh-Chih Yang, Hsinchu (TW); Randy Osborne, Beaverton, OR (US); and Win San Khwa, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 4, 2023, as Appl. No. 18/230,619.
Application 18/230,619 is a continuation of application No. 17/556,101, filed on Dec. 20, 2021, granted, now 11,762,732.
Application 17/556,101 is a continuation of application No. 16/535,787, filed on Aug. 8, 2019, granted, now 11,204,826, issued on Dec. 21, 2021.
Claims priority of provisional application 62/738,177, filed on Sep. 28, 2018.
Prior Publication US 2024/0028451 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G11C 11/16 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/102 (2013.01) [G11C 11/1655 (2013.01); G11C 29/52 (2013.01)] 20 Claims
OG exemplary drawing
 
10. A method, comprising:
providing a plurality of memory macros, each including an array of memory cells and a first ECC circuit;
providing a second ECC circuit communicatively coupled to each of the plurality of memory macros;
refreshing the memory arrays, including carrying out an error detection and correction operation, including carrying out a subset of steps in an error detection and correction operation by checking for data errors in the memory arrays with the first ECC circuits in the respective memory macros;
if any data error is detected by one of the plurality of the first ECC circuits, carrying out remainder steps of the error detection and correction operation in the second ECC circuit, the remainder steps including:
forwarding the detected data errors from the first ECC circuit to the second ECC circuit;
correcting the data error by the second ECC circuit; and
writing the corrected data to the respective memory array; and
if no data error is detected by one of the plurality of the first ECC circuits, ending the error detection and correction operation for the respective memory macro.