US 12,229,002 B2
Method and circuit for performing error detection on a clock gated register signal
Faizan Nazar, Hertfordshire (GB); and Kenneth Rovers, Hertfordshire (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Mar. 30, 2023, as Appl. No. 18/193,446.
Claims priority of application No. 2204690 (GB), filed on Mar. 31, 2022; and application No. 2204692 (GB), filed on Mar. 31, 2022.
Prior Publication US 2023/0384374 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G01R 31/317 (2006.01)
CPC G06F 11/1004 (2013.01) [G01R 31/31727 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An error detection circuit for performing a cyclic redundancy check on a clock gated register signal, the error detection circuit comprising:
a first register, wherein the first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal;
check bit processing logic configured to, in response to a control signal (b), update a second register with a check bit irrespective of whether the control signal (b) is a high value or a low value, wherein the control signal (b) is the same as the clock enabling signal; and
an error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.