US 12,228,994 B2
Method, apparatus, and system for calibrating a processor power level estimate
Sarthak Raina, Apex, NC (US); Sanjay Patel, Cary, NC (US); Hoan Tran, San Jose, CA (US); Mitrajit Chatterjee, Los Altos, CA (US); Abhishek Niraj, Cupertino, CA (US); and Anuradha Raghunathan, San Jose, CA (US)
Assigned to Ampere Computing LLC, Santa Clara, CA (US)
Filed by Ampere Computing LLC, Santa Clara, CA (US)
Filed on Sep. 10, 2021, as Appl. No. 17/472,319.
Prior Publication US 2023/0079292 A1, Mar. 16, 2023
Int. Cl. G06F 1/324 (2019.01); G01R 21/133 (2006.01); G06F 1/3206 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/324 (2013.01) [G01R 21/133 (2013.01); G06F 1/3296 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method for processor power management, comprising:
receiving first power information from a digital power meter (DPM) associated with a first component of a system-on-a-chip;
receiving second power information from a voltage regulator (VR) associated with the first component of the system-on-a-chip;
generating a power estimate value based on the first power information and the second power information; and
generating comparison information based on the first power information, the second power information, and a prior error representing a difference between a read power usage and an estimated power usage of the first component during a prior iteration of a calibration process, the first power information, the second power information, and the prior error all being direct inputs in generating the comparison information,
wherein a power to the first component or the system-on-a-chip is controlled based on the power estimate value and the comparison information.