US 12,228,961 B2
Memory system using asymmetric source-synchronous clocking
Frederick A. Ware, Los Altos Hills, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 8, 2024, as Appl. No. 18/629,138.
Application 18/629,138 is a continuation of application No. 17/368,046, filed on Jul. 6, 2021, granted, now 11,953,934.
Application 17/368,046 is a continuation of application No. 15/863,703, filed on Jan. 5, 2018, granted, now 11,068,017, issued on Jul. 20, 2021.
Application 15/863,703 is a continuation of application No. 14/114,863, granted, now 9,874,898, issued on Jan. 23, 2018, previously published as PCT/US2012/036861, filed on May 8, 2012.
Claims priority of provisional application 61/487,221, filed on May 17, 2011.
Prior Publication US 2024/0345618 A1, Oct. 17, 2024
Int. Cl. G06F 1/12 (2006.01); G06F 1/04 (2006.01); G06F 1/08 (2006.01); G11C 7/02 (2006.01); G11C 7/04 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G06F 1/06 (2006.01); G06F 1/10 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/04 (2013.01); G11C 7/02 (2013.01); G11C 7/04 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G06F 1/06 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
reference timing signal circuitry to provide a selectively-varying reference timing signal of a first frequency, the selectively-varying reference timing signal to exhibit, for a given waveform period, an edge defining a reference timing event;
a timing signal multiplier circuit, the timing signal multiplier circuit to receive the selectively-varying reference timing signal of the first frequency and produce, during the given waveform period, a multiplied timing signal that comprises a burst of consecutive edges defining multiple timing events corresponding to each reference timing event, the multiple timing events being separated by multiple bit time intervals; and
wherein the timing signal multiplier circuit is responsive to a change in the selectively-varying reference timing signal from the first frequency to a second frequency to alter a non-burst timing component of the multiplied timing signal without altering the multiple bit time intervals.