US 12,228,956 B2
Low headroom cascode bias circuit for cascode current mirrors
Andrew Weil, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 7, 2022, as Appl. No. 17/982,420.
Prior Publication US 2024/0152170 A1, May 9, 2024
Int. Cl. G05F 3/26 (2006.01)
CPC G05F 3/262 (2013.01) 14 Claims
OG exemplary drawing
 
1. A cascode bias circuit, comprising:
a first current source configured to provide a first current;
a second current source configured to provide a second current;
a first transistor having a drain coupled to the first current source, and a gate coupled to a gate of a first cascode transistor in a cascode current mirror;
a second transistor having a source coupled to a source of the first transistor and having a drain coupled to the second current source; and
a third transistor having a drain coupled to the source of the first transistor and coupled to a source of the second transistor, wherein the first current equals the second current, and wherein the cascode current mirror further includes a first diode-connected transistor arranged in series with the first cascode transistor and in series with a third current source that is configured to provide a third current that is twice as large as the first current, and
wherein a drain-to-source voltage of the second transistor matches a drain-to-source voltage of the first diode-connected transistor of the cascode current mirror.