| CPC G05F 1/575 (2013.01) [G05F 1/46 (2013.01)] | 20 Claims |
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1. A system-on-chip comprising:
a core comprising:
a header switch circuit including a plurality of header switches configured to transmit a power supply voltage, applied to a first power rail, as a supply voltage to a second power rail; and
a logic circuit configured to operate based on the supply voltage received from the second power rail;
a low-dropout (LDO) regulator configured to control on/off states of first header switches among the plurality of header switches based on a power state of the core and the supply voltage; and
a power management unit (PMU) configured to control power gating of the core, by collectively turning on or turning off on/off second header switches among the plurality of header switches to control a power-on state or a power-off state of the core.
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