a base substrate;

a plurality of gate lines located on the base substrate;

a metal layer located on a side of the plurality of gate lines away from the base substrate, wherein the metal layer comprises a plurality of data lines that extend in a first direction and are arranged in a second direction; the plurality of gate lines extend in the second direction and are arranged in the first direction; the first direction and the second direction intersect; the plurality of data lines and the plurality of gate lines intersect to define a plurality of pixel regions;

wherein at least one gate line comprises a gate line pad that comprises a protrusion protruding towards the pixel region relative to a portion of the gate line other than the gate line pad, and the metal layer located in the pixel region comprises a plurality of traces extending along at least part of a contour of the pixel region;

the plurality of traces comprise a plurality of first traces surrounding at least part of edges of the protrusion, and the plurality of first traces are connected end to end;

the array substrate further comprises a pixel electrode and a thin film transistor, wherein the thin film transistor comprises a first electrode, a gate electrode and a second electrode; the first electrode and the second electrode both overlap a film layer where the gate lines are located; the first electrode is electrically connected to the pixel electrode by a first connecting portion, and the second electrode is electrically connected to the data line; the first electrode, the second electrode and the first connecting portion are all structures in the metal layer;

the plurality of pixel regions comprise at least one first pixel region and at least one second pixel region; the first pixel region is a pixel region corresponding to the gate line pad, and the second pixel region is a pixel region corresponding to the portion of the gate line other than the gate line pad; at least part of the first connecting portion in the first pixel region surrounds at least part of edges of the protrusion; and a ratio of an area of an orthographic projection of the first connecting portion within the first pixel region on the base substrate to an area of an orthographic projection of the first connecting portion within the second pixel region on the base substrate is 0.8-1.2,

wherein the edges of the protrusion comprises a protrusion edge of which an extension direction is parallel neither to the first direction nor to the second direction; a number of the plurality of first traces is greater than or equal to 2, and a length of each first trace is L_i; an orthographic projection of each first trace on the base substrate is a first orthographic projection, an orthographic projection of the protrusion edge on the base substrate is a second orthographic projection; the first orthographic projection comprises a long edge extending in an extension direction thereof and close to the second orthographic projection; a minimum distance between the long edge and the second orthographic projection is d_i; an included angle between the long edge and the second orthographic projection is θ_i; and a first parameter C_pad in a capacitance between the first trace and the protrusion edge meets:

wherein the first parameter C_pad meets: 0.035≤C_pad≤5.