US 12,228,670 B2
Communication unit, integrated circuits and method for clock and data synchronization
Olivier Doaré, La Salvetat St Gilles (FR); Didier Salle, Toulouse (FR); Cristian Pavao Moreira, Frouzins (FR); Julien Orlando, Toulouse (FR); Jean-Stephane Vigier, Mondonville (FR); and Andres Barrilado Gonzalez, Toulouse (FR)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Jun. 21, 2019, as Appl. No. 16/447,985.
Claims priority of application No. 18305860 (EP), filed on Jul. 2, 2018.
Prior Publication US 2020/0003862 A1, Jan. 2, 2020
Int. Cl. G01S 7/00 (2006.01); G01S 7/35 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); H03L 7/08 (2006.01); H03M 1/12 (2006.01)
CPC G01S 7/003 (2013.01) [G06F 1/10 (2013.01); G06F 1/12 (2013.01); H03L 7/08 (2013.01); H03M 1/1245 (2013.01); G01S 7/35 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A radar unit comprising:
a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement, wherein the at least one slave device and the at least one master device are connected through transmission lines, and wherein the at least one master device and at least one slave device each include:
a demodulator circuit configured to receive a distributed reference clock signal that includes a system clock signal and a chirp start signal embedded in the system clock signal, and to produce a re-created system clock signal and a reproduced chirp start signal from the distributed reference clock signal;
a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal, and to create a master-slave clock signal based on the re-created system clock signal; and
an analog-to-digital converter, ADC, coupled to the reference phase locked loop and configured to use the master-slave clock signal and the reproduced chirp start signal to align respective sampling instants of a received representation of an echo signal, resulting from a transmitted frequency modulated signal, between each ADC of the at least one master device and at least one slave device.