US 12,228,619 B2
Through silicon via detection circuit and method
Weijie Cheng, Hefei (CN); and Onegyun Na, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INV, Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 31, 2022, as Appl. No. 17/823,583.
Application 17/823,583 is a continuation of application No. PCT/CN2022/094516, filed on May 23, 2022.
Claims priority of application No. 202210201963.2 (CN), filed on Mar. 2, 2022.
Prior Publication US 2023/0280416 A1, Sep. 7, 2023
Int. Cl. G01R 31/66 (2020.01); G01R 27/14 (2006.01); G01R 31/52 (2020.01)
CPC G01R 31/66 (2020.01) [G01R 27/14 (2013.01); G01R 31/52 (2020.01)] 17 Claims
OG exemplary drawing
 
1. A method for through silicon via detection, applied to a circuit for through silicon via detection, the circuit for through silicon via detection comprising a through silicon via to be tested, an equivalent adjustable resistor, and a reverse output circuit, a first terminal of the through silicon via to be tested being connected to a second terminal of the equivalent adjustable resistor, a second terminal of the through silicon via to be tested being grounded, and an input terminal of the reverse output circuit being connected to the first terminal of the through silicon via to be tested; the method comprising:
adjusting a resistance value of the equivalent adjustable resistor to a preset first resistance value, and keeping a voltage of a first terminal of the equivalent adjustable resistor at a preset voltage value, wherein the first resistance value is a maximum resistance value of an equivalent resistor corresponding to the through silicon via to be tested when the through silicon via to be tested is normal; and
determining whether the through silicon via to be tested is defective based on a signal output by an output terminal of the reverse output circuit, wherein
in response to a voltage of the first terminal of the through silicon via to be tested being greater than half of the preset voltage value, the output terminal of the reverse output circuit outputs a low level signal, and
in response to the voltage of the first terminal of the through silicon via to be tested being less than half of the preset voltage value, the output terminal of the reverse output circuit outputs a high level signal.