US 12,226,873 B2
System and method for processing silicon wafers
Andrei Istratov, Portland, OR (US); Tom Wu, Vancouver, WA (US); and Katharina Zahnweh, Burghausen (DE)
Assigned to SILTRONIC CORPORATION, Portland, OR (US)
Filed by Siltronic Corporation, Portland, OR (US)
Filed on Apr. 20, 2022, as Appl. No. 17/724,503.
Prior Publication US 2023/0339069 A1, Oct. 26, 2023
Int. Cl. B24B 49/02 (2006.01); B24B 9/06 (2006.01); B28D 5/00 (2006.01)
CPC B24B 49/02 (2013.01) [B24B 9/065 (2013.01); B28D 5/0064 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for processing a silicon wafer, the method comprising:
cutting an ingot to form a wafer;
extracting from measured shape data a cross-sectional profile, the cross-sectional profile passing through the center of the wafer and being aligned with a cutting direction of the ingot;
interpolating the measured shape data with a fixed and pre-determined step size;
fitting a first second-degree polynomial to the cross-sectional profile;
determining a residual profile by subtracting the first second-degree polynomial from the cross-sectional profile;
fitting a second second-degree polynomial to the residual profile using a sliding window of pre-determined width to determine a position, height, and curvature of each peak and valley of the residual profile;
determining a waviness parameter based on the position, height, and curvature of each peak and valley of the residual profile; and
further processing the wafer based on a comparison of the waviness parameter to a predetermined waviness threshold.