a memristor array, comprising a plurality of memristor units and connected to a plurality of source lines, a plurality of word lines and a plurality of bit lines, wherein each of the plurality of memristor units comprises a memristor;

an input circuit, configured to receive a plurality of first signals on a plurality of channels;

a first switching circuit, connected with the plurality of source lines;

a second switching circuit, connected with the plurality of word lines;

an output circuit, connected with the plurality of source lines; and

a control circuit, configured to:

control the first switching circuit to select at least one source line of the plurality of source lines to apply at least one first signal of the plurality of first signals to the at least one source line, respectively,

control the second switching circuit to select and activate at least one word line of the plurality of word lines to apply the at least one first signal to the memristor unit corresponding to the at least one word line, and

control the output circuit to output a plurality of second signals based on conductivity values of memristors of the memristor array, wherein the first switching circuit comprises a plurality of first selectors, and the second switching circuit comprises a plurality of second selectors,

wherein each of the plurality of first selectors is configured to select a corresponding source line of the plurality of source lines under a control of the control circuit to apply a corresponding first signal of the plurality of first signals to the corresponding source line,

wherein each of the plurality of second selectors is configured to select and activate a corresponding word line of the plurality of word lines under a control of the control circuit to apply a corresponding first signal of the at least one first signal to the memristor unit corresponding to the corresponding word line.