US 11,903,257 B2
Display panel and display apparatus
Jieliang Li, Xiamen (CN); and Jiaxian Liu, Shanghai (CN)
Assigned to Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed by Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed on Jan. 6, 2023, as Appl. No. 18/150,953.
Application 18/150,953 is a continuation of application No. 17/147,309, filed on Jan. 12, 2021, granted, now 11,574,978.
Claims priority of application No. 202011150331.5 (CN), filed on Oct. 23, 2020.
Prior Publication US 2023/0157077 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10K 59/121 (2023.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); H01L 27/12 (2006.01)
CPC H10K 59/1216 (2023.02) [G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); H10K 59/1213 (2023.02); G09G 2320/0626 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a base substrate; and
a driving array layer disposed on the base substrate and having functional layers and insulation layers,
wherein the driving array layer comprises:
a first transistor, wherein the first transistor comprises a first active layer comprising silicon;
a second transistor, wherein the second transistor comprises a second active layer comprising oxide semiconductor;
a first capacitor comprising a first plate and a second plate; and
a second capacitor comprising a third plate and a fourth plate,
wherein a first insulation layer is provided between the first plate and the second plate, and a second insulation layer is provided between the third plate and the fourth plate;
the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode and the first active layer, wherein the first gate electrode is located at a side of the first active layer away from the base substrate;
the second transistor comprises a second gate electrode, a third gate electrode, a second source electrode, a second drain electrode and the second active layer, wherein the second gate electrode is located between the second active layer and the base substrate; and the third gate electrode is located at a side of the second active layer away from the base substrate; and
the first gate electrode is located in a first metal layer, the second gate electrode is located in a second metal layer, and the third gate electrode is located in a third metal layer.