US 11,903,247 B2
Display device having polycrystalline silicon layer
Dong-Sung Lee, Hwaseong-si (KR); Seo Jong Oh, Seoul (KR); Byung Soo So, Yongin-si (KR); and Dong-min Lee, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Oct. 18, 2021, as Appl. No. 17/503,358.
Application 17/503,358 is a division of application No. 16/679,656, filed on Nov. 11, 2019, granted, now 11,164,919.
Claims priority of application No. 10-2018-0142225 (KR), filed on Nov. 19, 2018.
Prior Publication US 2022/0102447 A1, Mar. 31, 2022
Int. Cl. H10K 59/12 (2023.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H10K 59/12 (2023.02) [H01L 21/02057 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02675 (2013.01); H01L 29/66757 (2013.01); H01L 29/78675 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A display device, comprising:
a substrate;
a thin film transistor disposed on the substrate; and
a display element disposed on the thin film transistor,
wherein:
the thin film transistor comprises:
an active pattern disposed on the substrate and including a plurality of grains separated by grain boundaries, and having protrusions formed at the grain boundaries, the active pattern having a low surface roughness with a root-mean-square (RMS) value of about 4 nm or less, wherein the thin film transistor has a substantially uniform threshold voltage;
a gate insulation layer disposed on the active pattern, the gate insulation layer having a thickness in a range of about 30 nm to about 200 nm, and being protected from damage by the low surface roughness of the active pattern; and
a gate electrode disposed on the gate insulation layer.