US 11,903,223 B2
Thin film transistors and related fabrication techniques
Hernan A. Castro, Shingle Springs, CA (US); Stephen W. Russell, Boise, ID (US); and Stephen H. Tang, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 27, 2021, as Appl. No. 17/332,640.
Application 17/332,640 is a division of application No. 16/223,595, filed on Dec. 18, 2018, granted, now 11,043,496.
Prior Publication US 2021/0288050 A1, Sep. 16, 2021
Int. Cl. H10B 99/00 (2023.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/40 (2006.01); H01L 21/311 (2006.01); G11C 8/10 (2006.01); G11C 8/12 (2006.01); H01L 21/027 (2006.01); H10B 53/20 (2023.01); H10B 53/40 (2023.01); H10B 63/00 (2023.01)
CPC H10B 99/00 (2023.02) [H01L 29/401 (2013.01); H01L 29/41733 (2013.01); H01L 29/41741 (2013.01); H01L 29/42384 (2013.01); H01L 29/66742 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01); H01L 21/0274 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H10B 53/20 (2023.02); H10B 53/40 (2023.02); H10B 63/84 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a dielectric plug that extends through a stack that comprises a first layer and a second layer;
a semiconductor material, at the first layer, that surrounds the dielectric plug;
a gate electrode, at the second layer, that is in contact with and that surrounds the dielectric plug; and
an oxide material that is in contact with the dielectric plug and that is between the semiconductor material and the gate electrode.