US 11,903,222 B2
Memory device and method of manufacturing the same
Yumin Kim, Seoul (KR); Seyun Kim, Seoul (KR); Jinhong Kim, Seoul (KR); Soichiro Mizusaki, Suwon-si (KR); and Youngjin Cho, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 17, 2023, as Appl. No. 18/185,817.
Application 18/185,817 is a division of application No. 17/317,154, filed on May 11, 2021, granted, now 11,672,131.
Claims priority of application No. 10-2020-0113196 (KR), filed on Sep. 4, 2020.
Prior Publication US 2023/0225138 A1, Jul. 13, 2023
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/84 (2023.02) [H10B 63/34 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10N 70/841 (2023.02); H10N 70/8828 (2023.02); H10N 70/8833 (2023.02)] 5 Claims
OG exemplary drawing
 
1. A method of manufacturing a memory device, the method comprising:
forming a stack structure by repeatedly and alternately depositing a sacrificial layer and an isolating layer on a substrate;
forming a channel hole penetrating through the stack structure;
removing a portion of the sacrificial layer such that an inner surface of the channel hole has a concavo-convex shape in a first direction perpendicular to a stack direction of the stack structure;
sequentially forming a gate insulating layer, a channel layer, and a recording material layer on the inner surface of the channel hole;
depositing an insulating material in the channel hole;
forming a gate hole by removing all of a remaining portion of the sacrificial layer; and
depositing an electrode material in the gate hole.