US 11,903,219 B1
Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Debo Olaosebikan, San Francisco, CA (US); Tanay Gosavi, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/654,526.
Application 17/654,526 is a continuation of application No. 17/653,811, filed on Mar. 7, 2022.
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias; and
a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are planar capacitors that are arranged in a stacked and folded configuration.