US 11,903,208 B2
Semiconductor memory device and manufacturing method of the semiconductor memory device
Nam Kuk Kim, Yongin-si (KR); and Nam Jae Lee, Cheongju-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 15, 2022, as Appl. No. 17/841,348.
Application 17/841,348 is a division of application No. 16/787,517, filed on Feb. 11, 2020, granted, now 11,393,842.
Claims priority of application No. 10-2019-0091231 (KR), filed on Jul. 26, 2019.
Prior Publication US 2022/0310653 A1, Sep. 29, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 63/30 (2023.02); H10N 70/231 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a lower stack structure including a first semiconductor layer and a sacrificial layer which is disposed over the first semiconductor layer;
forming a channel layer extending from an inside of the first semiconductor layer to pass through the sacrificial layer and having a sidewall and a bottom surface covered by a memory layer, wherein the channel layer protrudes farther than the lower stack structure;
forming a gate stack structure on the lower stack structure to surround the channel layer;
removing the sacrificial layer to expose a part of the memory layer between the gate stack structure and the first semiconductor layer;
removing the part of the memory layer to separate the memory layer into a first memory pattern between the gate stack structure and the channel layer and a second memory pattern between the first semiconductor layer and the channel layer; and
replacing a part of the channel layer exposed between the first memory pattern and the second memory pattern by a doped semiconductor pattern.