US 11,903,200 B2
Semiconductor memory device and method for fabricating the semiconductor memory device
Yu Jeong Lee, Icheon-si (KR); Dae Hwan Yun, Icheon-si (KR); and Gil Bok Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 29, 2021, as Appl. No. 17/362,624.
Claims priority of application No. 10-2021-0018105 (KR), filed on Feb. 9, 2021.
Prior Publication US 2022/0254805 A1, Aug. 11, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01); H01L 23/31 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 23/3171 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a core pillar extended in a vertical direction;
a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering an other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region positioned under the first region; and
a channel passivation layer formed in the first region of the channel layer and abutting the core pillar,
wherein the channel layer of the first region has a smaller thickness than the channel layer of the second region, and
wherein an upper surface of the channel layer of the second region is contacted with bottom surfaces of the channel layer of the first region and the channel passivation layer.