US 11,903,195 B2
Openings layout of three-dimensional memory device
Jia He, Hubei (CN); Haihui Huang, Hubei (CN); Fandong Liu, Hubei (CN); Yaohua Yang, Hubei (CN); Peizhen Hong, Hubei (CN); Zhiliang Xia, Hubei (CN); Zongliang Huo, Hubei (CN); Yaobin Feng, Hubei (CN); Baoyou Chen, Hubei (CN); and Qingchen Cao, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Jan. 19, 2023, as Appl. No. 18/156,619.
Application 17/017,417 is a division of application No. 16/046,475, filed on Jul. 26, 2018, granted, now 10,804,283, issued on Oct. 13, 2020.
Application 18/156,619 is a continuation of application No. 17/017,417, filed on Sep. 10, 2020, granted, now 11,574,919.
Application 16/046,475 is a continuation of application No. PCT/CN2018/077716, filed on Mar. 1, 2018.
Claims priority of application No. 201710134033.9 (CN), filed on Mar. 7, 2017.
Prior Publication US 2023/0157020 A1, May 18, 2023
Int. Cl. H10B 43/20 (2023.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H01L 21/28 (2006.01)
CPC H10B 43/20 (2023.02) [H01L 29/40117 (2019.08); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a stack structure comprising a plurality of conductor layers and a plurality of insulating layers stacking alternately along a direction perpendicular to a top surface of the stack structure; and
an array of semiconductor channels within a first region of the stack structure, wherein each semiconductor channel of the array of semiconductor channels penetrates through the stack structure, and wherein:
the array of semiconductor channels comprises:
semiconductor channels in a first row and adjacent to a second region of the stack structure, wherein the second region is adjacent to the first region; and
semiconductor channels in a second row farther away from the second region than the semiconductor channels in the first row;
a first length of a top surface of each of the semiconductor channels in the first row is greater than a second length of a top surface of each of the semiconductor channels in the second row, wherein the first length and the second length are along a first direction parallel to the top surface of the stack structure and pointing from the second region to the first region;
the first length of the top surface of each of the semiconductor channels in the first row is greater than a first width of the top surface of each of the semiconductor channels in the first row, wherein the first width is along a second direction parallel to the top surface of the stack structure and perpendicular to the first direction; and
the second length of the top surface of each of the semiconductor channels in the second row is substantially the same as a second width of the top surface of each of the semiconductor channels in the second row, wherein the second width is along the second direction.