US 11,903,194 B2
Integrated circuit
Ya-Chun Tsai, Hsin-Chu (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Nov. 17, 2021, as Appl. No. 17/529,027.
Prior Publication US 2023/0157018 A1, May 18, 2023
Int. Cl. G11C 5/02 (2006.01); H10B 43/10 (2023.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); H10B 41/10 (2023.01)
CPC H10B 43/10 (2023.02) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); H10B 41/10 (2023.02)] 14 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
at least one first memory block and at least one second memory block respectively disposed on two sides of the integrated circuit, wherein each of the at least one first memory block and the at least one second memory block includes a memory cell array having a three-dimensional architecture; and
a pad disposing area, wherein the at least one first memory block and the at least one second memory block are symmetrically disposed about the pad disposing area, a plurality of pads are disposed in the pad disposing area, and the pads are respectively electrically coupled to the at least one first memory block and the at least one second memory blocks,
wherein each of the at least one first memory block and the at least one second memory block comprises a control circuit generating a control signal to control an access operation of the corresponding memory cell array,
wherein the control circuit of the at least one first memory block and the control circuit of the at least one second memory block are symmetrically disposed about the pad disposing area.