CPC H10B 41/30 (2023.02) [H01L 21/76802 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 29/42324 (2013.01); H01L 29/6653 (2013.01); H10B 41/10 (2023.02); H10B 41/40 (2023.02); H10B 41/42 (2023.02); H01L 23/485 (2013.01); H01L 29/6656 (2013.01)] | 20 Claims |
1. An integrated chip, comprising:
a first gate structure over a substrate and laterally surrounded by a first sidewall spacer, wherein the first gate structure protrudes outward from a top of the first sidewall spacer;
a second gate structure over the substrate and laterally surrounded by a second sidewall spacer that extends to a top of the second gate structure, wherein the first gate structure has a first height that is larger than a second height of the second gate structure; and
wherein the first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.
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