US 11,903,192 B2
Semiconductor device and method of manufacturing
Josh Lin, Tainan (TW); Chia-Ta Hsieh, Tainan (TW); Chen-Ming Huang, Tainan (TW); and Chi-Wei Ho, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 21, 2021, as Appl. No. 17/381,599.
Application 16/202,602 is a division of application No. 15/694,393, filed on Sep. 1, 2017, granted, now 10,263,004, issued on Apr. 16, 2019.
Application 17/381,599 is a continuation of application No. 16/829,145, filed on Mar. 25, 2020, granted, now 11,075,212.
Application 16/829,145 is a continuation of application No. 16/202,602, filed on Nov. 28, 2018, granted, now 10,629,605, issued on Apr. 21, 2020.
Claims priority of provisional application 62/539,601, filed on Aug. 1, 2017.
Prior Publication US 2021/0351195 A1, Nov. 11, 2021
Int. Cl. H10B 41/30 (2023.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H10B 41/10 (2023.01); H10B 41/40 (2023.01); H10B 41/42 (2023.01); H01L 23/485 (2006.01)
CPC H10B 41/30 (2023.02) [H01L 21/76802 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 29/42324 (2013.01); H01L 29/6653 (2013.01); H10B 41/10 (2023.02); H10B 41/40 (2023.02); H10B 41/42 (2023.02); H01L 23/485 (2013.01); H01L 29/6656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first gate structure over a substrate and laterally surrounded by a first sidewall spacer, wherein the first gate structure protrudes outward from a top of the first sidewall spacer;
a second gate structure over the substrate and laterally surrounded by a second sidewall spacer that extends to a top of the second gate structure, wherein the first gate structure has a first height that is larger than a second height of the second gate structure; and
wherein the first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.