US 11,903,189 B2
Three-dimensional memory and fabricating method thereof
Bo-Feng Young, Taipei (TW); Sai-Hooi Yeong, Zhubei (TW); Chih-Yu Chang, New Taipei (TW); Han-Jong Chia, Hsinchu (TW); Chenchen Jacob Wang, Hsinchu (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 9, 2020, as Appl. No. 16/924,903.
Prior Publication US 2022/0013532 A1, Jan. 13, 2022
Int. Cl. H10B 41/27 (2023.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H10B 41/30 (2023.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01)
CPC H10B 41/27 (2023.02) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); H01L 29/0669 (2013.01); H01L 29/42392 (2013.01); H10B 41/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional memory, comprising:
a plurality of memory cells arranged in a plurality of levels stacked in a first direction, and divided into a plurality of groups, wherein each of the groups of the memory cells is formed in respective level of the levels;
a plurality of word lines extending along a second direction and formed in the same level under the memory cells, wherein the second direction is perpendicular to the first direction;
a plurality of bit lines, wherein each of the bit lines comprises a plurality of sub-bit lines formed in the levels; and
a plurality of source lines, wherein each of the source lines comprises a plurality of sub-source lines formed in the levels,
wherein in each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between the columns.