US 11,903,121 B2
Printed circuit board design for high speed application
Nan-Jang Chen, Hsinchu (TW)
Assigned to MediaTek Inc., Hsinchu (TW)
Filed by MediaTek Inc., Hsinchu (TW)
Filed on Jul. 6, 2022, as Appl. No. 17/858,445.
Application 17/858,445 is a division of application No. 16/929,651, filed on Jul. 15, 2020, abandoned.
Application 16/929,651 is a division of application No. 16/581,734, filed on Sep. 24, 2019, granted, now 10,772,191, issued on Sep. 8, 2020.
Application 16/581,734 is a division of application No. 15/877,396, filed on Jan. 23, 2018, granted, now 10,485,095, issued on Nov. 19, 2019.
Application 15/877,396 is a continuation in part of application No. 13/408,062, filed on Feb. 29, 2012, granted, now 9,949,360, issued on Apr. 17, 2018.
Claims priority of provisional application 61/451,283, filed on Mar. 10, 2011.
Prior Publication US 2022/0353985 A1, Nov. 3, 2022
Int. Cl. H05K 1/02 (2006.01); H05K 1/11 (2006.01); H01P 3/08 (2006.01); H05K 1/05 (2006.01); H05K 1/18 (2006.01)
CPC H05K 1/0219 (2013.01) [H01P 3/08 (2013.01); H05K 1/0224 (2013.01); H05K 1/0227 (2013.01); H05K 1/05 (2013.01); H05K 1/0218 (2013.01); H05K 1/0298 (2013.01); H05K 1/11 (2013.01); H05K 1/18 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A printed circuit board, comprising:
a substrate having a top surface and a bottom surface;
a reference plane embedded in the substrate and adjacent to the top surface;
a first signal net disposed within a specific region on the top surface of the substrate;
a second signal net in close proximity to the first signal net and disposed within the specific region on the top surface of the substrate;
an outermost insulating layer disposed on the top surface of the substrate to cover the substrate, the first signal net and the second signal net, wherein the outmost insulating layer comprises an opening to expose a portion of the second signal net;
a conductive layer disposed in the opening and on the outermost insulating layer corresponding to the specific region in which the first signal net and the second signal net are arranged, such that the conductive layer overlaps with the first signal net; and
a fifth signal net embedded in the substrate and between the reference plane and the outermost insulating layer, wherein a top side and a bottom side of the fifth signal net are covered by the substrate,
a second reference plane embedded in the substrate and adjacent to the bottom surface;
a third signal net and a fourth signal net being in close proximity to each other and disposed within a second specific region on the bottom surface of the substrate;
a bottom outermost insulating layer disposed on the bottom surface of the substrate to cover the substrate, the third signal net and the fourth signal net, wherein the bottom outmost insulating layer comprises a second opening to expose a portion of the fourth signal net; and
a bottom conductive layer disposed in the second opening and on the bottom outermost insulating layer corresponding to the second specific region in which the third signal net and the fourth signal net are arranged, such that the bottom conductive layer overlaps with the third signal net.