US 11,902,997 B2
Unicast data transmission on a downlink common burst of a slot using mini-slots
Alexandros Manolakos, Escondido, CA (US); and Jing Jiang, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Dec. 2, 2022, as Appl. No. 18/074,128.
Application 18/074,128 is a continuation of application No. 16/810,072, filed on Mar. 5, 2020, granted, now 11,558,890.
Application 16/810,072 is a continuation of application No. 15/693,025, filed on Aug. 31, 2017, granted, now 10,616,914, issued on Apr. 7, 2020.
Claims priority of provisional application 62/443,397, filed on Jan. 6, 2017.
Prior Publication US 2023/0199783 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 72/23 (2023.01); H04W 72/12 (2023.01); H04W 72/1273 (2023.01); H04L 5/00 (2006.01); H04W 72/0446 (2023.01)
CPC H04W 72/23 (2023.01) [H04L 5/003 (2013.01); H04L 5/0037 (2013.01); H04L 5/0044 (2013.01); H04L 5/0051 (2013.01); H04L 5/0055 (2013.01); H04L 5/0094 (2013.01); H04W 72/1273 (2013.01); H04W 72/0446 (2013.01); H04W 72/12 (2013.01)] 20 Claims
OG exemplary drawing
 
11. An apparatus, comprising:
a memory; and
one or more processors coupled to the memory, the one or more processors and the memory being configured to:
be scheduled to receive first data in a control portion, the control portion comprising a number of symbols in a slot, the control portion comprising a frequency band utilized for control information;
be scheduled to receive second data in a second portion of the slot, the second portion of the slot being outside of the number of symbols, the first data and the second data being received on a second frequency band;
transmit an acknowledgement to acknowledge both the first data and the second data.