CPC H04N 19/132 (2014.11) [H04N 19/174 (2014.11); H04N 19/176 (2014.11); H04N 19/70 (2014.11)] | 14 Claims |
1. A video decoding apparatus comprising:
a memory; and
at least one processor connected to the memory, the at least one processor configured to:
parse number information related to a number of explicit slices each having its height explicitly signaled within a tile of a current picture from a bitstream;
parse height information related to heights of explicit slices each having its height explicitly signaled from the bitstream based on the number information;
derive a number of slices within the tile based on the number information and the height information;
generate prediction samples by performing prediction on a current block of the current picture based on one of the slices within the tile;
generate reconstructed samples based on the prediction samples; and
generate a reconstructed picture for the current picture based on the reconstructed samples,
wherein a number of syntax elements in the height information is equal to the number of the explicit slices specified by the number information,
wherein, based on the number of explicit slices being equal to n, heights of a 0-th slice to an (n−1)-th slice within the tile are derived based on the syntax elements in the height information,
wherein a height of an n-th slice within the tile is derived based on the height of the (n−1)-th slice, and
wherein a height of a last slice within the tile is derived based on a remaining height after subtracting the heights of other slices within the tile from a height of the tile.
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