CPC H04L 9/3278 (2013.01) [G06F 21/75 (2013.01); G11C 11/419 (2013.01); H03K 3/0315 (2013.01)] | 20 Claims |
12. A physical unclonable function (PUF) generator comprising:
a PUF cell array that comprises a plurality of bit cells, wherein the plurality of bit cells each comprises at least two access transistors, at least one enable transistor, at least two storage nodes;
a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine first logical states of each of the plurality of bit cells, and based on the first logical states of the plurality of bit cells, to generate a first PUF output, wherein the PUF control circuit is coupled to at least one power supply voltage and at least one corresponding zero voltage reference;
at least one noise injector coupled to the PUF cell array and the PUF control circuit, wherein the at least one noise injector is configured to introduce noise into the plurality of bit cells to cause the plurality of bit cells to have respective second logical states, wherein the PUF control circuit generates a second PUF output based on the second logical states;
a compare circuit for comparing the second PUF output with the first PUF output; and
a mask array for storing at least one location of at least one unstable bit cell, respectively, the at least one unstable bit cell having different states between the first and second PUF outputs; and
a filter configured to exclude at least one logical state of the at least one unstable bit cell to generate the PUF signature.
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