US 11,902,412 B2
Fault attack resistant cryptographic systems and methods
Jeremy Dubeuf, La Ciotat (FR); Yann Yves Rene Loisel, La Ciotat (FR); and Frank Lhermet, Roquevaire (FR)
Assigned to Maxim Integrated Products, Inc., San Jose, CA (US)
Filed by Maxim Integrated Products, Inc., San Jose, CA (US)
Filed on May 26, 2022, as Appl. No. 17/824,912.
Application 17/824,912 is a continuation of application No. 16/596,590, filed on Oct. 8, 2019, granted, now 11,349,635.
Claims priority of application No. 1859337 (FR), filed on Oct. 9, 2018.
Prior Publication US 2022/0286270 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/00 (2022.01); H04L 9/08 (2006.01); G06F 7/58 (2006.01)
CPC H04L 9/004 (2013.01) [H04L 9/0869 (2013.01); G06F 7/588 (2013.01); H04L 2209/08 (2013.01); H04L 2209/12 (2013.01)] 18 Claims
OG exemplary drawing
 
9. A non-transitory computer-readable medium or media comprising one or more sequences of instructions which, when executed by at least one processor, causes steps to be performed comprising:
using a secret in a computation that outputs an expected number, the secret causes the computation to output an incorrect result in the event that the computation has been subject to one or more manipulations such that, in the event of an attack, no information is revealed from which confidential information may be extracted;
comparing the expected number to a number calculated by the computation;
based on the comparison, determining whether the computation is valid;
in response to the computation being invalid, generating an error indicating that the computation has been subject to the one or more manipulations; and
in response to the computation being valid, removing an effect of the secret from the expected number to output a correct result.