CPC H04L 63/1408 (2013.01) [B60R 16/0231 (2013.01); H04L 1/08 (2013.01); H04L 12/40143 (2013.01); H04L 67/12 (2013.01); G06N 20/00 (2019.01); H04L 2012/40273 (2013.01)] | 21 Claims |
1. A computing apparatus comprising:
a processor coupled to a communication bus; and
memory storing instructions, which when executed by the processor configure the apparatus to:
identify a first message from a plurality of messages transmitted on the communication bus as a low priority message;
cause overlap in arrival time between the low priority message and a second message from the plurality of messages;
determine whether the low priority message and the second message from the plurality of messages originated from a first electronic control unit (ECU) coupled to the communication bus, the second message a higher priority message than the low priority message, responsive to the overlap in arrival time; and
associate a message identification (MID) of the low priority message and an MID of the higher priority message to the first ECU.
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