CPC H04L 27/261 (2013.01) [H04B 7/0413 (2013.01); H04L 1/0041 (2013.01); H04L 1/0061 (2013.01); H04L 27/22 (2013.01); H04L 27/2613 (2013.01); H04W 84/12 (2013.01); H03M 5/12 (2013.01); H04L 25/4904 (2013.01); H04L 27/14 (2013.01); H04L 27/144 (2013.01); H04L 27/148 (2013.01); H04L 27/1563 (2013.01); H04L 27/2273 (2013.01); H04L 27/2331 (2013.01); H04L 27/2332 (2013.01); H04L 27/2647 (2013.01); H04L 2027/0028 (2013.01); H04N 21/426 (2013.01); H04Q 1/46 (2013.01); H04W 28/06 (2013.01)] | 6 Claims |
1. An apparatus, comprising:
at least one processor;
at least one memory including computer program code, the memory and the computer program code being configured to, when executed by the processor, cause the apparatus to perform at least the following:
receive a Physical Layer Convergence Procedure (PLCP) Protocol Data Unit (PPDU), the PPDU comprising:
a first field including a first symbol that is mapped onto a first binary phase shift keying (BPSK) constellation;
a second field including a second symbol and a third symbol immediately after the second symbol, the second symbol being mapped onto the first BPSK constellation, and the third symbol being mapped onto a second BPSK constellation and rotated by 90° counter-clockwise relative to the second symbol; and
a training field immediately after the second field,
wherein the second symbol includes an indicator indicating a Single User-Multiple Input Multiple Output (SU-MIMO) PPDU or a multi user-MIMO (MU-MIMO) PPDU, and the third symbol includes a cyclic redundancy check (CRC) for the second symbol and at least a portion of the third symbol.
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