US 11,902,015 B2
Multi-channel signal synchronization system, circuit, and method
Junzhou Luo, Suzhou (CN); Chaomin Fang, Suzhou (CN); Bo Yan, Suzhou (CN); Yue Wang, Suzhou (CN); Tiejun Wang, Suzhou (CN); and Weisen Li, Suzhou (CN)
Assigned to RIGOL TECHNOLOGIES CO., LTD., Jiangsu (CN)
Filed by RIGOL TECHNOLOGIES CO., LTD., Jiangsu (CN)
Filed on Oct. 14, 2022, as Appl. No. 17/966,133.
Application 17/966,133 is a continuation of application No. PCT/CN2021/087347, filed on Apr. 15, 2021.
Claims priority of application No. 202010315258.6 (CN), filed on Apr. 21, 2020.
Prior Publication US 2023/0032250 A1, Feb. 2, 2023
Int. Cl. H04J 3/06 (2006.01)
CPC H04J 3/0638 (2013.01) 10 Claims
OG exemplary drawing
 
1. A multi-channel signal synchronization system, comprising a clock signal generation module, a synchronization signal generation module, and at least two signal receiving modules, wherein
the clock signal generation module is configured to generate a first clock signal and transmit the first clock signal to the synchronization signal generation module;
the synchronization signal generation module is configured to generate a synchronization signal based on the first clock signal output by the clock signal generation module, and to transmit the synchronization signal to the clock signal generation module;
the clock signal generation module is further configured to generate a second clock signal based on the synchronization signal fed back by the synchronization signal generation module, and to transmit the second clock signal to the at least two signal receiving modules; and
the synchronization signal generation module is further configured to transmit the synchronization signal to the at least two signal receiving modules,
wherein the clock signal generation module is configured to generate an intermediate clock signal according to a received reference clock signal and generate a second clock signal according to the intermediate clock signal and the synchronization signal, and
wherein the clock signal generation module is configured to input the synchronization signal and the intermediate clock signal into a gating clock unit to obtain the second clock signal.